A 41.7 MS/s 2.4 ps-rms-jitter Time Converter With 4-Core Interleaved Analog-Multiplexed Architecture
Abstract: This paper presents a single channel time-to-amplitude converter (TAC) that exploits an on-chip time-interleaving technique to reach an unprecedented conversion rate. Implemented in a 350-nm ...
Abstract: A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be ...
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